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outside","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"an alpha of 0.5 at three references tells the eight alpha tests apart","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the alpha tests' names read as the fixed suite's cases do","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the standard four samples sit at (6,2) (14,6) (2,10) (10,14) sixteenths","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a rectangle to a pixel's centre covers 0x5 of the standard four","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a rectangle to a pixel's centre covers 0x2 of the standard two","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a rectangle to a pixel's centre covers 0x3a of the standard eight","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a rectangle past a pixel covers every one of eight","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"every sample at the centre leaves a pixel cut a quarter in uncovered","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the standard four put sample 2 inside a pixel cut a quarter in","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the coverage suite's own four split a pixel at its centre as 0x3","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the grid pattern splits even columns as 0x3 and odd ones as 0xc in both rows","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a quarter, a half, three quarters and all read table entries 3, 7, 11, 15","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"every modulated channel is a whole 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{"type":"case","suite":"reference","name":"gradients of one, two, four and eight texels give lambdas 0 to 3 exactly","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"one texel along x and four along y give lambda 2","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"nearest mip filtering keeps level 0 up to lambda one half and stops at the last level","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"13/32 lands at least 3/16 of a texel from a boundary on every level","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"an offset in a level's own texels reads another texel than one in level nought's on levels 1 to 3","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"lambda 1.25 blends level 1's 1019 and level 2's 2001 to 1264.5, a float exactly","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"lists, strips, fans, quads, quad strips and polygons make the triangles and provoking vertices OpenGL's table gives","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"line loops close, line strips do not, and quads and polygons drawn as lines show their outlines alone","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"an index list splits at its restart index, and indexed triangles add the vertex offset","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the topology suite's quads, quad strip, polygon and fan cover exactly their rectangles","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"every edge where the topology suite's colour changes keeps a twentieth of a pixel from every pixel centre","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a line loop's closing side is judged drawn, a line strip's clear, and a quad's diagonal clear when drawn as lines","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a missed restart in the topology suite's strips and fans draws pixels the cases judge clear","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the copy suite's pictures give every texel a value of its own, and the full texels every combination of nought and full","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the copy suite's channels of nought and full become the bytes each format holds them in","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"a flipped, layered, scaled or padded copy puts each texel where worked out by hand","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the vertex suite's layouts give hand-worked floats and its vertices read where worked out by hand","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the svc suite's kernel results are the codes the console returns","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"an svc case's line names a kernel result and gives a code it does not know","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"frint's roundings of a single worked out by hand","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"the estimate tables and the unsigned estimates give hand-worked values","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"frecpe, frsqrte and frecpx give hand-worked singles and flags","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"half precision under AHP and DN gives hand-worked values and flags","tier":"none","result":"pass","detail":""} {"type":"case","suite":"reference","name":"fmax, fmin, fmaxnm and fminnm order hand-worked NaNs and noughts","tier":"none","result":"pass","detail":""} {"type":"note","text":"journal: launch 2 resumes the run; the program ended inside cpu case \"sm4ekey and sm4e give the SM4 standard's worked example\": that case is skipped as crashed and goes on the crash list, and step cpu runs again from its start"} {"type":"case","suite":"cpu","name":"clz counts each of sixteen 8-bit lanes","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"clz counts each of eight 16-bit lanes","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"clz counts each of four 32-bit lanes","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sdiv and udiv by zero give zero, 32 and 64 bits","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frintx rounds to nearest even and raises inexact","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frinta rounds halfway cases away from zero","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sqshlu saturates 8, 16 and 64-bit lanes and sets QC","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fcvtzs and fcvtzu with 64 fraction bits scale by 2^64","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sm4ekey and sm4e give the SM4 standard's worked example","tier":"none","result":"skip","reason":"crashed","detail":"the program ended inside it earlier in this run; it is on the crash list (sdmc:/edenprobe/crashes), and the mode word retry runs it in a later run"} {"type":"case","suite":"cpu","name":"48 new straight-line blocks with 33 live registers leave the state worked out apart","tier":"exact","result":"pass","detail":""} {"type":"note","text":"cpu compile: 48 blocks of 160 operations, first calls 82 us, second calls 2 us, 1659 ns a block to compile"} {"type":"case","suite":"cpu","name":"sqrshl and uqrshl round, shift and saturate lanes of every width","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sqdmlal, sqdmlsl and sqdmull double, accumulate and saturate","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sqrshrn, uqrshrn and sqrshrun round and narrow scalars","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frecpe gives the Arm ARM's reciprocal estimate of singles of every class, flags too","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frsqrte gives the reciprocal square root estimate of singles of every class, flags too","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"urecpe and ursqrte give the unsigned estimates, and all ones below their range","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frecpx gives the reciprocal exponent, the largest for noughts and denormals","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fcvtn and fcvtl with AHP take exponent 31 as a number and saturate past 131008","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fcvtn keeps a NaN's payload's top bits, and gives the default NaN with DN set","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fmax, fmin, fmaxnm and fminnm order NaNs, noughts and denormals as the Arm ARM does","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sshl and ushl shift lanes of every width by a signed byte","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"srshl and urshl round lanes of every width shifted right","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"sqshl and uqshl by a register saturate every width and set QC","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"crc32b, h, w and x update four accumulators bit for bit","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"crc32cb, h, w and x update four accumulators with the Castagnoli polynomial","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frintn, frintp, frintm, frintz and frinta round sixteen singles each their own way","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frinti rounds by each of FPCR's four modes and raises nothing","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"frintx rounds by each of FPCR's four modes and raises inexact where it rounds","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fmadd and fmsub round once, keep exact results exact and do not overflow midway","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fmadd gives the default NaN for nought times infinity plus a quiet NaN","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fcmeq, fcmge and fcmgt mask NaN lanes false and raise invalid as each compare must","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"fadd, fsub, fmul and fdiv keep NaN payloads and nought's sign lane by lane and raise their flags","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"a NaN stored from a b, h, s, d or q register keeps its bits and touches no other byte","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"ldxp and stxp swap a 128-bit pair","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"stxp after clrex fails and leaves the pair","tier":"exact","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"cntfrq_el0 says 19.2 MHz and 100 ms asleep counts at that rate","tier":"position","result":"pass","detail":""} {"type":"case","suite":"cpu","name":"mrs cntvct_el0 reads a virtual count that moves with the physical one","tier":"exact","result":"pass","detail":""}